codejunkie99/gateflow-cli

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SystemVerilog RTL Design

codejunkie99/gateflow-cli

4

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SystemVerilog Verification Provides verification methodology, SVA assertion patterns, coverage techniques, and testbench templates. Use when the…

codejunkie99/gateflow-cli

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SystemVerilog Development This skill should be used when the user asks to 'design a module', 'write SystemVerilog', 'implement an FSM', 'create…

codejunkie99/gateflow-cli

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SystemVerilog Lint Fixing This skill should be used when the user mentions 'lint error', 'width mismatch', 'inferred latch', 'undriven signal',…

codejunkie99/gateflow-cli

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SystemVerilog Testbench Patterns This skill should be used when the user asks to 'write a testbench', 'test this module', 'add assertions', 'create te…

codejunkie99/gateflow-cli

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GateFlow Behavior This skill should be used when the user is working on any SystemVerilog, Verilog, HDL, RTL, FPGA, or ASIC development…

codejunkie99/gateflow-cli

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VCD Waveform Analysis This skill should be used when the user mentions 'waveform', 'VCD file', 'simulation results', 'signal trace', 'debug…

codejunkie99/gateflow-cli

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