Source

smithery/mamemame777

2 skills · 0 combined installs

Skills from this source

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Skill

Source

8W Activity

Installs

assertion-design SystemVerilog Assertions (SVA) as executable specifications. Use when defining timing requirements, protocol specific…

smithery/mamemame777

rtl-debugging RTL design debugging methodology and reasoning process. Use when investigating test failures, assertion violations, s…

smithery/mamemame777